Lina Irawan
In a move that signals a seismic shift in the trajectory of global semiconductor engineering, IBM and Siemens have announced a high-stakes research collaboration. The partnership is dedicated to the industrialization of "nanostack," IBM’s pioneering three-dimensional transistor architecture. By integrating IBM’s cutting-edge semiconductor physics with Siemens’ industry-leading electronic design automation (EDA) and manufacturing simulation expertise, the two technology giants aim to bridge the gap between experimental laboratory breakthroughs and the mass-market commercialization of angstrom-scale chips.
This collaboration is not merely an incremental update to existing processes; it is a fundamental reimagining of how computing power is constructed. As the industry approaches the physical limits of traditional two-dimensional scaling, the transition to the Z-axis represents the most significant architectural evolution since the invention of the integrated circuit.
The Core Innovation: Moving Beyond the Flatland of Silicon
For over six decades, the semiconductor industry has adhered to the principles of planar scaling, expanding the footprint of transistors across the X and Y axes. This approach, which fueled the rapid advancement of the digital age, is now hitting a wall of diminishing returns. As transistors shrink to atomic scales, the "real estate" available on a silicon wafer has become a critical bottleneck for performance and power efficiency.
What is Nanostack?
IBM’s nanostack architecture effectively moves the industry into the third dimension. By vertically stacking nanosheet-based transistors, engineers can achieve density levels previously considered impossible. The analogy used by IBM is strikingly intuitive: just as urban developers maximize land value by constructing skyscrapers rather than sprawling single-story homes, nanostack enables chip designers to stack functional layers on a fixed footprint.
At the current 7-angstrom node, this vertical approach yields nearly double the transistor density per unit area compared to the standard 2nm nanosheet technology that defined the state-of-the-art as recently as 2021. By stacking these layers, IBM has created a design capable of housing nearly 100 billion transistors on a chip no larger than a human fingernail.
Chronology of the Angstrom Era
The journey toward the angstrom era has been a rapid succession of milestones that have kept IBM at the forefront of silicon research.
- 2021: The 2nm Breakthrough: IBM unveiled the world’s first 2nm chip, utilizing nanosheet technology to achieve unprecedented performance-per-watt efficiency.
- Early 2026: Proof of Concept: IBM successfully demonstrated the viability of the 3D nanostack architecture in a laboratory setting, confirming that vertical transistor stacking was not just theoretical, but physically feasible.
- June 2026: The 7-Angstrom Milestone: IBM officially disclosed its breakthrough in the 7-angstrom node, marking the company’s entry into sub-nanometre chip fabrication—a threshold once thought to be decades away.
- Late 2026: The Siemens Partnership: Recognizing the immense complexity of manufacturing 3D structures at this scale, IBM formalized its partnership with Siemens to leverage digital twin technology and advanced lithography optimization.
- Present – 2030 (Projected): The collaborative focus shifts to refining manufacturing workflows, perfecting lithography techniques for future generations, and preparing the infrastructure for commercial-scale production.
The Synergy of Expertise: Why Siemens?
The challenge of manufacturing a nanostack chip is exponentially more difficult than that of a standard planar chip. When working at the sub-nanometre level, even the slightest deviation in atomic placement can lead to device failure.
Siemens enters this partnership bringing its sophisticated EDA portfolio, which serves as the "architectural blueprint" for modern silicon. Through this collaboration, the two firms are focusing on:
- Advanced Virtual Modeling: Using Siemens’ software, engineers can build "digital twins" of nanostack devices. These virtual models allow for the simulation of device physics before a single wafer is etched.
- Lithography Optimization: By simulating how light and chemical processes interact at the 7-angstrom scale, the partners can refine the manufacturing paths required to align vertical layers with perfect precision.
- Process Simulation: Identifying potential fabrication obstacles—such as heat dissipation within a 3D stack or material interaction between layers—is now a computational task handled by Siemens’ simulation tools.
This "tightly coupled co-optimization" is essential. In the angstrom era, the boundary between design and manufacturing has effectively vanished; the chip is the design, and the design is the manufacturing process.
Official Perspectives: Shaping the Future of Compute
The leadership from both organizations has expressed a clear vision for why this partnership is critical for the next decade of AI and global compute requirements.
Huiming Bu, Vice President of Silicon Technology R&D at IBM:
"Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D. It represents a new paradigm for the semiconductor industry and a path forward for the logic scaling needed to support AI and other emerging technologies over the coming decade. We aren’t just building faster chips; we are building a new foundation for the future of global data processing."
Ankur Gupta, Executive Vice President of the IC Portfolio at Siemens EDA:
"Scaling semiconductors into the angstrom era demands tightly coupled co-optimisation between device physics, EDA design software, and manufacturing. As physical AI places extraordinary demands on silicon architecture, IBM’s 3D nanostack design represents a pivotal leap forward. Our goal is to ensure that this leap is not just a laboratory success, but a manufacturing reality."
Implications for the Global Tech Landscape
The move to 3D stacking has profound implications that extend far beyond the laboratory.
Power Efficiency and Sustainability
The primary benefit of vertical stacking is the reduction of interconnect lengths. In a traditional 2D chip, signals must travel across long horizontal distances, consuming energy and creating latency. By moving transistors into a stack, the "distance" between logic gates is shortened. This is expected to drive massive improvements in energy efficiency, allowing for more powerful AI models to run on mobile devices and edge servers without the massive power draw currently required.
Enabling the AI Revolution
Artificial Intelligence is currently starved for compute. The training of Large Language Models (LLMs) requires millions of transistors working in unison. By significantly increasing the density of transistors, nanostack allows for higher memory bandwidth and lower latency—both of which are critical for the next generation of generative AI and autonomous systems.
A New Manufacturing Paradigm
The partnership signals that the future of semiconductor manufacturing is software-defined. Because physical experimentation is so costly and time-consuming at the sub-nanometre scale, the company that wins the race will be the one that can most accurately simulate the fabrication process. Siemens’ involvement suggests that the industry is moving toward a "Simulation-First" approach, where the fabrication process is perfected in the cloud before the first physical mask is ever created.
Economic and Strategic Resilience
For IBM, this partnership is a strategic maneuver to maintain its relevance as a top-tier semiconductor innovator. For the broader industry, it provides a roadmap for how to sustain "Moore’s Law" in an era where traditional silicon physics were threatening to hit a plateau. As nations and corporations race to secure domestic semiconductor supply chains, the ability to manufacture 7-angstrom and smaller chips—and to do so with high yields through advanced simulation—will become a cornerstone of technological sovereignty.
Conclusion
The IBM and Siemens collaboration marks a critical transition point in human history. We are moving from an era of expansion—where we simply made chips wider and flatter—to an era of density and depth. By embracing the Z-axis, these two giants are not just solving a temporary engineering problem; they are unlocking a new dimension of performance that will power the next fifty years of computing. As the industry watches this 3D transition unfold, the nanostack architecture stands as a testament to the fact that when physical boundaries are reached, human ingenuity simply builds upwards.
Lina Hope
Rifan Muazin
